1. Field of the Invention
The present invention relates generally to a user equipment (UE) in an asynchronous Wideband Code Division Multiple Access (WCDMA) communication system, and in particular, to an apparatus and method for compensating for distortion caused by the phase slew of a frame reference signal in the output of a Finite Impulse Response (FIR) filter.
2. Description of the Related Art
Universal Mobile Telecommunication Service (UMTS), a third generation mobile communication system based on European asynchronous mobile communication systems, Global System for Mobile communications (GSM), and General Packet Radio Services (GPRS), consistently provides a service that allows mobile subscribers and computer users to transmit packet-based text, digital voice and video data, and multimedia data at or above 2 Mbps all over the world. With the introduction of virtual connection, which is defined as a packet-switched connection using a packet protocol e.g., an Internet protocol (IP), UMTS promises a connection to any end point in the network.
Since Code Division Multiple Access (CDMA) performs digital processes including user identification and coding/decoding in small units of data called a chip (e.g., for a chip rate of 1.2299 Mcps, one chip is 813.8 ns in duration), synchronization between a base station and a mobile station is very important. A synchronous mobile communication system synchronizes base stations using GPS receivers. In comparison, an asynchronous mobile communication system like UMTS is characterized by asynchronous Node Bs and the sharing of the same timing information between a Node B and User Equipments (UEs) in a cell associated with the Node B. UE, which accesses the Wideband Code Division Multiple Access (WCDMA) system, transmits or receives data according to reception and transmission (Rx and Tx) frame reference signals from a corresponding Node B.
FIG. 1 is a timing diagram illustrating an example of Tx and Rx frame reference signals in UE that accesses a conventional asynchronous CDMA communication system.
Referring to FIG. 1, Rx and Tx frame reference signals 102 and 104, respectively, are generated every radio frame of 10 ms. To accurately detect signals when it moves from one cell to another cell, the UE maintains timing that offers the best reception rate by advancing or retarding the Rx frame reference signal 102 by a predetermined reference chip unit, usually a ⅛ chip. Reference numerals 106 and 110 denote the advanced Rx frame reference signal and the retarded Rx frame reference signal, respectively. The Tx frame reference signal 104 is advanced or retarded by the same amount (e.g., a predetermined reference chip unit such as a ⅛ chip) because a 1024-chip interval is kept between the Rx frame reference signal 102 and the Tx frame reference signal 104. Reference numerals 108 and 112 denote the advanced Tx frame reference signal and the retarded Tx frame reference signal, respectively. In the UE, therefore, a receiver notifies a modulator of a transmitter of an advanced or retarded point of the Rx frame reference signal 102 in units of reference chips, so that the Tx frame reference signal 104 can compensate for the reference chips.
FIG. 2 is a block diagram illustrating an example of a digital modulator in the UE that accesses the conventional asynchronous CDMA communication system.
Referring to FIG. 2, a digital modulator 200 comprises a channelization code spreader 206 for multiplying Dedicated Physical Data Channel (DPDCH) traffic data 202 and Dedicated Physical Control Channel (DPCCH) control data 204 by a predetermined spreading code, a gain controller 208 for multiplying the spread data by a predetermined gain G, a scrambling code spreader 210 for scrambling the gain-controlled data by multiplying it by a predetermined scrambling code, and an Square Root Raised Cosine (SRRC) filter 212 for outputting I and Q channel transmission data, TX_DATA_I and TX_DATA_Q by limiting the bandwidth of the scrambled signal and suppressing interference from adjacent frequency channels.
The channelization code spreader 206, the gain controller 208, and the scrambling code spreader 210 process data at a 1-chip sampling rate, while the SRRC filter 212 processes data at a ¼-chip sampling rate. Since the SRRC filter 212 outputs 4 over-samples per chip, it is influenced by the phase slew of the Tx frame reference signal. Therefore, the SRRC filter 212 needs to compensate for timing affected by the phase slew of the Tx frame reference signal.
Uplink DPCCH and DPDCH data all use the same frame timing. The DPCCH/DPDCH frame transmission occurs 1024 chips after a signal is detected in the first DPCCH/DPDCH detected path on a corresponding downlink. If the reference timing is changed, the UE advances or retards the Tx frame reference signal with a resolution of a ⅛ chip every 140 ms, thereby slowly compensating for timing differences. The ⅛ chip is a reference chip unit by which the phase of the frame reference signal is slewed.
The SRRC filter 212 is an FIR filter usually used in a communication device adopting a digital modulation such as Phase Shift Keying (PSK) or Quadrature Amplitude Modulation (QAM). Real-time processing in the SRRC filter 212 is very important because the final output of the SRRC filter 212 is transmitted to an analog stage via a digital to analog converter (DAC). For application of the SRRC filter 212 to an asynchronous CDMA communication system, ⅛ chip-based timing compensation is essential.
The 48-tap SRRC filter 212 includes 48 delays, 48 multipliers, and a summer for summing the 48 products in the conventional asynchronous WCDMA communication system. The implementation of all these devices in the UE occupies too much hardware space. Thus, a UE designer usually reduces the number of filtering taps by using calculator sharing and time sharing.
FIG. 3 is a block diagram illustrating an example of the structure of a conventional SRRC filter. Referring to FIG. 3, an SRRC filter 300 includes serially-connected delays 302, 304, 306, 308 and 310 each for delaying in-phase (I channel) data, I_CH_DATA by one chip, serially-connected delays 312, 314, 316, 318 and 320 each for delaying quadrature-phase (Q channel) data, Q_CH_data by one chip, multiplexers (MUXs) 322, 324, 326, 328 and 330 each for selecting I or Q channel data every ⅛ chip, a coefficient MUX 342 for selecting a filtering coefficient for the selected I/Q channel data every ¼ chip, 4-pipeline multipliers 332, 334, 336 and 340 each for multiplying the selected I/Q channel data by the selected coefficient, a 3-pipe line summer 344 for summing the outputs of the multipliers 332, 334, 336 and 340, a selector 346 for alternately selecting the I and Q channel sums every ⅛ chip, and a delay 348 for delaying the I channel data received from the selector 346 by a ⅛ chip so that the final I and Q channel values, FILTER_OUTPUT_I and FILTER_OUTPUT_Q can be output at the same time.
As illustrated in FIG. 1, a minimum signal processing unit time is 10 ms in the WCDMA system. Hence, it is important to detect the boundary of a 10-ms radio frame. To control the SRRC filter 300 having the above-described configuration, ⅛ chip-based count signals synchronized with a frame reference signal are required. Thus, the SRRC filter 300 generates a ⅛ chip count value, CHIP×8_COUNT using a ⅛ chip (CHIP×8) counter 350. CHIP×8_COUNT ranges from 0 to 307199, to detect the boundary of a 10 ms-frame.
Using CHIP×8_COUNT from the CHIP×8 counter 350, count signals, CHIP×8_COUNT[0], [1], [2] can be generated for the SRRC filter 300. Since the lower 3 bits of CHIP×8_COUNT can be used as a 1 chip-based count value, the MUXs 322, 324, 326, 328 and 330 use the least significant bit (LSB) of the ⅛ chip count, CHIP×8_COUNT[0] as a select signal and the MUX 342 uses the second and third LSBs of the ⅛ chip count, CHIP×8_COUNT [1], [2] as select signals.
As mentioned earlier, due to the 1024-chip interval between the Rx frame reference signal for the downlink DPDCH and DPCCH and the Tx frame reference signal for the uplink, if the Rx frame reference signal is advanced or retarded (i.e. phase slew) along the time axis, the Tx frame reference signal is also moved the same amount to maintain the 1024-chip interval.
Although CHIP×8_COUNT is increased by 1 every ⅛ chip, it is increased by 2 in the case of a phase advance, and kept unchanged in the case of a phase retardation. Then, the MUXs 322, 324, 326, 328 and 330 may select I and Q channel data in a wrong order (e.g. I, Q, I, Q, Q, I, Q, I, . . . ). Moreover, because all multiplications and additions for SRRC filtering cannot be performed for a ⅛ chip, a pipeline structure having a length of 1 chip must be used and thus the selector 346 exchanges I and Q channel data in relation to the previous input. These two phenomenons cause I/Q output distortion for one chip.
FIG. 4 is a timing diagram illustrating an example of an output distortion when a phase advance in the conventional SRRC filter occurs, particularly a timing of a signal in each logic experiencing an exchange between I and Q outputs for 1 chip when a ⅛ chip phase advance occurs. For conciseness, the input timing of I_CH_DATA and Q_CH_DATA, the delay timing of the I and Q channel delays 302 and 312, the output timing of the MUX 322; the output timing of the MUX 342, the multiplication timing of the 4-pipeline multiplier 332 in each pipeline stage, the summation timing of the 3-pipeline summer 344 in each pipeline stage, and the output timing of the delay 348 after the selector 346 are shown in units of a ⅛ chip cycle.
Referring to FIG. 4, at the phase advance, CHIP×8_COUNT[2:0] jumps from 0 to 2. As I and Q channel data are exchanged in the MUX 322, Q_1, I_2, I_2, I_2, Q_2, I_2, Q_2, . . . and pass through the pipelines of the multiplier 332 and the summer 344 for 1 chip, the selector 346 produces I and Q channel data in an exchanged order, thereby leading to a 1-chip output distortion. That is, FILTER_OUTPUT_I and FILTER_OUTPUT_Q are exchanged for 1 chip, as indicated in black stripes.
FIG. 5 is a timing diagram illustrating an example of an output distortion when a phase retardation in the conventional SRRC filter occurs, particularly a timing of a signal in each logic experiencing an exchange between I and Q outputs for 1 chip when a ⅛ chip phase retardation occurs. Referring to FIG. 5, at the phase retardation, CHIP×8_COUNT[2:0] is maintained as 0 for two ⅛ chips, and the I and Q channel information are exchanged as Q_1, I_2, I_2, I_2, Q_2, I_2, Q_2, . . . in the MUX 322. Thus, an exchange occurs between FILTER_OUTPUT_I and FILTER_OUTPUT_Q for 1 chip, as indicated in black stripes.